CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 66

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Sleep and Watchdog
9.4
9.4.1
The Sleep bit, in the CPU_SCR0 register, is an input into the
sleep logic circuit. This circuit is designed to sequence the
device into and out of the hardware sleep state. The hard-
ware sequence to put the device to sleep is shown in
Figure 9-1
1. Firmware sets the Sleep bit in the CPU_SCR0 register.
2. The CPU issues a Bus Request Acknowledge (BRA) on
3. The sleep logic waits for the following negative edge of
66
The Bus Request (BRQ) signal to the CPU is immedi-
ately asserted: This is a request by the system to halt
CPU operation at an instruction boundary.
the following positive edge of the CPU clock.
the CPU clock and then asserts a system-wide Power
Down (PD) signal. In
the system-wide power down signal is asserted.
and is defined as follows.
Timing Diagrams
Sleep Sequence
CPUCLK
SLEEP
BRQ
BRA
IOW
Figure
Firmware write to
immediate BRQ.
PD
the SLEEP bit
causes an
9-1, the CPU is halted and
CPUCLK edge.
CPU captures
BRQ on next
Figure 9-1. Sleep Sequence
with a BRA.
responds
The system-wide PD signal controls three major circuit
blocks: the Flash memory module, the Internal Main Oscilla-
tor (6/12 MHz oscillator that is also called the IMO), and the
bandgap voltage reference. These circuits transition into a
zero power state. The only operational circuits on the PSoC
device are the ILO, the bandgap refresh circuit, and the sup-
ply voltage monitor circuit.
CPU
bandgap are powered down.
The 6/12 MHz system clock
CPUCLK, PD is asserted.
is halted; the Flash and
On the falling edge of
PSoC CY8C20x34 TRM, Version 1.0