CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 47

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a
hardware resource in PSoC mixed-signal array devices, to change program execution to a new address without regard to the
current task being performed by the code being executed. For a complete table of the Interrupt Controller registers, refer to
the
the
5.1
A block diagram of the PSoC Interrupt Controller is shown in
pending interrupts.
The sequence of events that occur during interrupt process-
ing are.
1. An interrupt becomes active, either because (a) the
2. The current executing instruction finishes.
3. The internal interrupt routine executes, taking 13 cycles.
PSoC CY8C20x34 TRM, Version 1.0
5.
interrupt condition occurs (for example, a timer expires),
(b) a previously posted interrupt is enabled through an
update of an interrupt mask register, or (c) an interrupt is
pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag
register.
During this time, these actions occur:
“Summary Table of the Core Registers” on page
Register Reference chapter on page
GPIO, etc.)
Interrupt
Source
(Timer,
Architectural Description
Interrupt Controller
1
INT_CLRx Write
Interrupt Taken
D
or
R
Q
Mask Bit Setting
Figure 5-1. Interrupt Controller Block Diagram
139.
Interrupt
INT_MSKx
Posted
24. For a quick reference of all PSoC registers in address order, refer to
Interrupt
Pending
Figure
Encoder
Priority
5-1, illustrating the concepts of posted interrupts and
The PCH, PCL, and Flag register (CPU_F) are
The CPU_F register is then cleared. Since this clears
The PCH (PC[15:8]) is cleared to zero.
The interrupt vector is read from the interrupt control-
pushed onto the stack (in that order).
the GIE bit to ‘0’, additional interrupts are temporarily
disabled.
ler and its value is placed into PCL (PC[7:0]). This
sets the program counter to point to the appropriate
address in the interrupt table (for example, 001Ch for
the GPIO interrupt).
CPU_F[0]
GIE
Interrupt Vector
Interrupt
Request
M8C Core
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