CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 106

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

I2C Slave
14.4.4
When a Byte Complete interrupt occurs, the PSoC device firmware must respond with a write to the I2C_SCR register to con-
tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see
ing” on page
I2C_SCR register; otherwise, a stall occurs. Once stalled, the IO write releases the stall. The setup time between data output
and the next rising edge of SCL is always N-1 clocks.
106
Slave Stall Timing
105). As illustrated in
(Synchronized)
I/O WRITE
SDA_OUT
SCL_OUT
SCL_IN
CLOCK
SCL
Figure
14-9, firmware has until one clock after the falling edge of SCL_IN to write to the
No STALL
Figure 14-9. Slave Stall Timing
1 Clocks
STALL
PSoC CY8C20x34 TRM, Version 1.0
N-1 Clocks
“Status Tim-