CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 104
CY8C20X34
Manufacturer Part Number
CY8C20X34
Description
Technical Reference Manual (TRM)
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C20X34.pdf
(218 pages)
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I2C Slave
14.4.2
Figure 14-5
sampling, N=4; for 32 times sampling, N=12. N is derived from the half-bit rate sampling of eight and 16 clocks, respectively,
minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks).
104
SDA_OUT
CLK CTR
SDA_IN
CLOCK
SCL_IN
SHIFT
illustrates basic input output timing that is valid for both 16 times sampling and 32 times sampling. For 16 times
Basic IO Timing
SCL
N
0
Figure 14-5. Basic Input/Output Timing
1
2
. . .
. . .
. . .
. . .
. . .
. . .
N
0
1
PSoC CY8C20x34 TRM, Version 1.0
2
. . .
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N
0
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