CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 119

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

is not selected, this behavior must be implemented in firm-
ware with IO writes to the port drive register.
18.1.3.1
The following are usability exceptions for the SPI Slave
function.
1. The SPI_RXR (Rx Buffer) register is not writeable.
2. The SPI_TXR (Tx Buffer) register is not readable.
18.1.3.2
The SPIS block has a selection of two interrupt sources:
Interrupt on TX Reg Empty (default) or interrupt on SPI
18.2
These registers are associated with the SPI and are listed in address order. The register descriptions have an associated reg-
ister table showing the bit structure for that register. For a complete table of SPI registers, refer to the
System Resource Registers” on page
Data Registers
18.2.1
The SPI Transmit Data Register (SPI_TXR) is the SPI’s
transmit data register.
18.2.2
The SPI Receive Data Register (SPI_RXR) is the SPI’s
receive data register. A write to this register will clear the RX
Reg Full status bit in the Control register (SPI_CR).
PSoC CY8C20x34 TRM, Version 1.0
0,29h
0,2Ah
Address
Address
Register Definitions
SPI_TXR
SPI_RXR
SPI_TXR Register
SPI_RXR Register
Usability Exceptions
Block Interrupt
Name
Name
Bit 7
Bit 7
90.
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Complete (same selection as the SPIM). Mode bit 1 in the
function register controls the selection.
If SPI Complete is selected as the block interrupt, the control
register must still be read in the interrupt routine so that this
status bit is cleared; otherwise, no subsequent interrupts are
generated.
18.1.4
All pin inputs are double synchronized to SYSCLK by
default. Synchronization can be bypassed by setting the
BYPS bit in the SPI_CFG register.
Bits 7 to 0: Data[7:0]. These bits encompass the SPI
Transmit register. They are discussed by function type in
Table 18-2
For additional information, refer to the
page
Bits 7 to 0: Data[7:0]. These bits encompass the SPI
Receive register. They are discussed by function type in
Table 18-2
For additional information, refer to the
page
Data[7:0]
Data[7:0]
142.
143.
Bit 3
Bit 3
and
and
Input Synchronization
Table
Table
Bit 2
Bit 2
18-3.
18-3.
Bit 1
Bit 1
“Summary Table of the
SPI_RXR register on
SPI_TXR register on
Bit 0
Bit 0
Access
Access
W : 00
R : 00
SPI
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