CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 105

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

(Synchronized)
14.4.3
Figure 14-6
plete, which occurs on the positive edge of the ninth clock
(byte + ACK/NACK) in Transmit mode and on the positive
edge of the eighth clock in Receive mode. There is a maxi-
mum of three cycles of latency due to the input synchro-
nizer/filter circuit. As shown, the interrupt occurs on the
clock following a valid SCL positive edge input transition
(after the synchronizers). The Address bit is set with the
same timing but only after a slave address has been
received. The LRB (Last Received Bit) status is also set with
the same timing but only on the ninth bit after a transmitted
byte.
Figure 14-6. Byte Complete, Address, LRB Timing
PSoC CY8C20x34 TRM, Version 1.0
SCL_IN
CLOCK
SCL
IRQ
illustrates the interrupt timing for Byte Com-
Transmit: Ninth positive edge SCL
Receive: Eighth positive edge SCL
Status Timing
and INTERRUPT
and INTERRUPT
START DETECT
Misplaced Start
Misplaced Stop
STOP DETECT
(Synchronized)
(Synchronized)
BUS ERROR
BUS ERROR
3 Cycles
Latency
Max
SDA_IN
SDA_IN
CLOCK
CLOCK
SDA
SDA
SCL
SCL
Figure 14-8. Bus Error Interrupt Timing
STOP DETECT
(Synchronized)
Figure 14-7
(and the interrupt occurs) two clocks after the synchronized
and filtered SDA line transitions to a ‘1’, when the SCL line is
high.
Figure 14-7. Stop Status and Interrupt Timing
Figure 14-8
Error status (and Interrupt) occurs one cycle after the inter-
nal Start or Stop Detect (two cycles after the filtered and syn-
chronized SDA input transition).
and STATUS
STOP IRQ
SDA_IN
CLOCK
SDA
SCL
illustrates the timing for bus error interrupts. Bus
shows the timing for Stop Status. This bit is set
I2C Slave
105