CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 169
CY8C20X34
Manufacturer Part Number
CY8C20X34
Description
Technical Reference Manual (TRM)
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C20X34.pdf
(218 pages)
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20.3.29 MVW_PP
This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
36
Bit
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
MVW_PP: 0,D5h
Access : POR
Bit Name
in the RAM Paging chapter .
Page Bit
Name
MVI Write Page Pointer Register
7
6
Description
Bit determines which SRAM page a MVI Write instruction operates on.
0b
1b
Note A value beyond the available SRAM, for a specific PSoC device, should not be set.
SRAM Page 0
SRAM Page 1
5
4
3
2
0,D5h
Register Definitions on page
1
Page Bit
RW : 0
MVW_PP
0,D5h
0
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