CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 9

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

PSoC CY8C20x34 TRM, Version 1.0
15. Internal Voltage References ............................................................................................ 107
16. System Resets ................................................................................................................. 109
17. POR and LVD ................................................................................................................... 115
18. SPI ................................................................................................................................... 117
14.4
15.1
15.2
16.1
16.2
16.3
16.4
16.5
17.1
17.2
18.1
18.2
14.3.3
Timing Diagrams ....................................................................................................................103
14.4.1
14.4.2
14.4.3
14.4.4
Architectural Description ........................................................................................................107
Register Definitions ...............................................................................................................108
15.2.1
Architectural Description ........................................................................................................109
Pin Behavior During Reset.....................................................................................................109
16.2.1
16.2.2
Register Definitions ...............................................................................................................110
16.3.1
16.3.2
Timing Diagrams ...................................................................................................................112
16.4.1
16.4.2
16.4.3
16.4.4
Power Modes ........................................................................................................................114
Architectural Description ........................................................................................................115
Register Definitions ...............................................................................................................115
17.2.1
17.2.2
Architectural Description ........................................................................................................117
18.1.1
18.1.2
18.1.3
18.1.4
Register Definitions ...............................................................................................................119
18.2.1
18.2.2
18.2.3
18.2.4
18.1.1.1
18.1.2.1
18.1.2.2
18.1.3.1
18.1.3.2
18.2.2.1
18.2.2.2
18.2.3.1
18.2.4.1
I2C_DR Register .................................................................................................103
Clock Generation .................................................................................................103
Basic IO Timing....................................................................................................104
Status Timing .......................................................................................................105
Slave Stall Timing ................................................................................................106
BDG_TR Register ...............................................................................................108
GPIO Behavior on Power Up ...............................................................................109
GPIO Behavior on External Reset .......................................................................110
CPU_SCR1 Register ..........................................................................................110
CPU_SCR0 Register .......................................................................................... 111
Power On Reset ..................................................................................................112
External Reset ....................................................................................................112
Watchdog Timer Reset .......................................................................................112
Reset Details........................................................................................................114
VLT_CR Register ................................................................................................115
VLT_CMP Register .............................................................................................116
SPI Protocol Function .........................................................................................117
SPI Master Function ...........................................................................................118
SPI Slave Function .............................................................................................118
Input Synchronization ..........................................................................................119
SPI_TXR Register ...............................................................................................119
SPI_RXR Register ..............................................................................................119
SPI_CR Register .................................................................................................121
SPI_CFG Register ..............................................................................................122
SPI Protocol Signal Definitions ..........................................................118
Usability Exceptions...........................................................................118
Block Interrupt....................................................................................118
Usability Exceptions...........................................................................119
Block Interrupt....................................................................................119
SPI Master Data Register Definitions ................................................120
SPI Slave Data Register Definitions ..................................................120
SPI Control Register Definitions ........................................................121
SPI Configuration Register Definitions ..............................................122
Contents
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