CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 54

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

General Purpose IO (GPIO)
All IO contain the capability to connect to an internal analog
bus. This is described in detail in the
Multiplexer chapter on page
Certain pins contain an option to bypass the normal data
path and output from an internal source. An example is I2C
outputs. These are described in
6.1.2
One of the basic operations of the GPIO ports is to allow the
M8C to send information out of the PSoC device and get
information into the M8C from outside the PSoC device.
This is accomplished by way of the port data register
(PRTxDR). Writes from the M8C to the PRTxDR register
store the data state, one bit per GPIO. In the standard non-
bypass mode, the pin drivers drive the pin in response to
this data bit, with a drive strength determined by the Drive
mode setting. The actual voltage on the pin depends upon
the Drive mode and the external load.
The M8C reads the value of a port by reading the PRTxDR
register address. When the M8C reads the PRTxDR register
address, the current value of the pin voltage is translated
into a logic value and returned to the M8C. Note that the pin
voltage can represent a different logic value than the last
value written to the PRTxDR register. This is an important
distinction to remember in situations such as the use of a
read modify write to a PRTxDR register. Examples of read
modify write instructions include AND, OR, and XOR.
Here is an example of how a read modify write, to a
PRTxDR register, could have an unexpected and even inde-
terminate result in certain systems. Consider a scenario
where all bits of Port 1 on the PSoC device are in the strong
0 resistive 1 Drive mode; so that in some cases, the system
the PSoC is in may pull down one of the bits by an external
driver.
mov
and
In the first line of code above, writing a 0xFF to the port
causes the PSoC to drive all pins high through a resistor.
This does not affect any bits that happen to be strongly
driven low by the system the PSoC is in. However, in the
second line of code, it cannot guarantee that only bit 7 is the
one set to a strong 0 (zero). Because the AND instruction
will first read the port, any bits that are currently driven low
externally will be read as a ‘0’. These zeros will then be writ-
ten back to the port. When this happens, the pin will go in to
a strong 0 state; therefore, if the external low drive condition
ends in the system, the PSoC will keep the pin value at a
logic 0.
54
reg[PRT1DR], 0xFF
reg[PRT1DR], 0x7F
Digital IO
83.
“Data Bypass” on page
IO Analog
56.
6.1.3
Analog signals can pass into the PSoC device core from
PSoC device pins through a resistive path. For analog sig-
nals, the GPIO block is typically configured into a High
Impedance Analog Drive mode (High-Z). This mode turns
off the Schmitt trigger on the input path, which may reduce
power consumption and decrease internal switching noise
when using a particular IO as an analog input.
All modes, except High Impedance Analog, allow digital
inputs. The most useful digital input modes are Resistive
Pull Up (DM1, DM0 = 00b with Data = 1) or a fully high
impedance input using open drain (DM1, DM0 = 11b with
Data = 1).
6.1.4
Port 1 has two differences from the other GPIO ports. It has
stronger high drive and it has an option for regulating all out-
puts to a 3V level when in strong drive mode. Refer to the
device datasheet for the different current sourcing specifica-
tions of Port 1.
By setting the REG_EN bit in the IO_CFG register, Port 1
can be configured to drive strong high to a regulated 3V
level, when device Vdd is above 3V. If REG_EN is set low,
Port 1 pins drive to Vdd in strong drive mode.
In Resistive High Drive mode ([DM1, DM0] = 00), the pins
pull up to the chip Vdd level regardless of the regulator set-
ting for this port. Only Strong Drive mode allows for the out-
puts to be driven to the regulated level. When the REG_EN
bit is set high, pins configured for strong drive will drive to
3V, while those in resistive pull-up mode will drive to Vdd.
Analog and Digital Inputs
Port 1 Distinctions
PSoC CY8C20x34 TRM, Version 1.0