CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 30

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

CPU Core (M8C)
2.5
The M8C has a total of seven instruction formats that use
instruction lengths of one, two, and three bytes. All instruc-
tion bytes are fetched from the program memory (Flash),
using an address and data bus that are independent from
the address and data buses used for register and RAM
access.
While examples of instructions are given in this section,
refer to the PSoC Designer Assembly Language User Guide
for detailed information on individual instructions.
2.5.1
Many instructions, such as some of the MOV instructions,
have single-byte forms because they do not use an address
or data as an operand. As shown in
instructions use an 8-bit opcode. The set of one-byte
instructions can be divided into four categories, according to
where their results are stored.
Table 2-3. One-Byte Instruction Format
The first category of one-byte instructions are those that do
not update any registers or RAM. Only the one-byte NOP
and SSC instructions fit this category. While the program
counter is incremented as these instructions execute, they
do not cause any other internal M8C registers to update, nor
do these instructions directly affect the register space or the
RAM address space. The SSC instruction causes SROM
code to run, which modifies RAM and the M8C internal reg-
isters.
The second category contains only the two PUSH instruc-
tions. The PUSH instructions are unique because they are
the only one-byte instructions that modifies a RAM address.
These instructions automatically increment the SP.
The third category contains only the HALT instruction. The
HALT instruction is unique because it is the only a one-byte
instruction that modifies a user register. The HALT instruc-
tion modifies user register space address FFh (CPU_SCR0
register).
The final category for one-byte instructions are those that
cause updates of the internal M8C registers. This category
holds the largest number of instructions:
DEC
SWAP
ters or SRAM to update.
30
8-Bit Opcode
,
. These instructions can cause the A, X, and SP regis-
INC
Byte 0
,
Instruction Formats
MOV
One-Byte Instructions
,
POP
,
RET
,
RETI
,
Table
RLC
ASL
,
2-3, one-byte
ROMX
,
ASR
,
,
CPL
RRC
,
,
2.5.2
The majority of M8C instructions are two bytes in length.
While it is possible to divide these instructions into catego-
ries identical to the one-byte instructions, this does not pro-
vide a useful distinction between the three two-byte
instruction formats that the M8C uses.
Table 2-4. Two-Byte Instruction Formats
The first two-byte instruction format, shown in the first row of
Table 2-4,
JACC
uses only four bits for the instruction opcode, leaving 12 bits
to store the relative destination address in a two’s-comple-
ment form. These instructions can change program execu-
tion to an address relative to the current address by -2048 or
+2047.
The second two-byte instruction format, shown in the sec-
ond row of
Source Immediate addressing mode (see the PSoC
Designer Assembly Language User Guide). The destination
for these instructions is an internal M8C register, while the
source is a constant value. An example of this type of
instruction is
The third two-byte instruction format, shown in the third row
of
addressing modes. Here is a list of the addressing modes
that use this third two-byte instruction format:
For more information on addressing modes see the PSoC
Designer Assembly Language User Guide.
4-Bit Opcode 12-Bit Relative Address
8-Bit Opcode
8-Bit Opcode
Table 2-4,
Source Direct (
Source Indexed (
Destination Direct (
Destination Indexed (
Source Indirect Post Increment (
Destination Indirect Post Increment (
,
INDEX
Byte 0
is used by short jumps and calls:
Table 2-4,
ADD A, 7
Two-Byte Instructions
is used by a wide range of instructions and
,
JC
ADD A, [7]
,
8-Bit Data
8-Bit Address
ADD A, [X+7]
JNC
is used by instructions that employ the
ADD [7], A
PSoC CY8C20x34 TRM, Version 1.0
ADD [X+7], A
.
,
JNZ
Byte 1
,
JZ
)
. This instruction format
MVI A, [7]
)
)
MVI [7], A
)
CALL
)
,
JMP
)
,