CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 128

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SPI
18.3.3
Enable/Disable Operation. As soon as the block is config-
ured for SPI Slave and before enabling, the MISO output is
set to idle at logic 1. Both the enable bit must be set and the
SS_ asserted (either driven externally or forced by firmware
programming) for the block to output data. When enabled,
the primary output is the MSb or LSb of the shift register,
depending on the LSb First configuration in bit 7 of the Con-
trol register. The auxiliary output of the SPIS is always
forced into tri-state.
Since the SPIS has no internal clock, it must be enabled
with setup time to any external master supplying the clock.
Setup time is also required for a TX Buffer register write,
before the first edge of the clock or the first falling edge of
SS_ depending on the mode. This setup time must be
assured through the protocol and an understanding of the
timing between the master and slave in a system.
128
At the falling edge of SS_, MISO
SPIS Timing
transitions from an IDLE (high)
to output the first bit of data.
TX REG EMPTY
SCLK (MODE 0)
SCLK (MODE 1)
SCLK (internal)
RX REG FULL
User writes first byte to the
TX Buffer register in
advance of transfer.
MISO
SS_
Figure 18-9. Typical SPIS Timing in Modes 0 and 1
First input
latched.
D7
bit is
User writes the next byte
to the TX Buffer register.
First
Shift
D6
D5
Last bit of received data is valid
on this edge and is latched into
When the block is disabled, the MISO output reverts to its
idle '1' state. All internal state is reset (including CR0 status)
to its configuration-specific reset state, except for DR0,
DR1, and DR2 which are unaffected.
Normal Operation. Typical timing for a SPIS transfer is
shown in
marily being used as a receiver, the RX Reg Full (polling
only) or SPI Complete (polling or interrupt) status may be
used to determine when a byte has been received. In this
way, the SPIS operates identically with the SPIM. However,
there are two main areas in which the SPIS operates differ-
ently: 1) SPIS behavior related to the SS_ signal, and 2) TX
data queuing (loading the TX Buffer register).
the RX Buffer register.
D2
Figure 18-9
D1
and
D0
PSoC CY8C20x34 TRM, Version 1.0
Figure
D7
18-10. If the SPIS is pri-
D7
D6