HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 105

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.4.2
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception handling according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The priority level of the user break interrupt and H-UDI is 15. IRQ interrupt and on-chip
peripheral module interrupt priority levels can be set freely using the interrupt priority level setting
registers A to E (IPRA to IPRE) of the INTC as shown in table 5.8. The priority levels that can be
set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRE, see section 6.3.4, Interrupt
Priority Registers A to E (IPRA to IPRE).
Table 5.8
5.4.3
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception handling begins. In interrupt exception handling, the
CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted
interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set
in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched
from the exception handling vector table for the accepted interrupt, and program execution
branches to that address and the program starts. For details on the interrupt exception handling, see
section 6.6, Interrupt Operation.
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Interrupt Priority
Interrupt Exception Handling
Interrupt Priority
Priority Level
16
15
15
0 to 15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level. Can be masked.
Fixed priority level.
Set with interrupt priority level setting registers
A through E (IPRA to IPRE).
Rev. 6.00 Jun. 12, 2007 Page 73 of 610
Section 5 Exception Handling
REJ09B0131-0600