HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 439

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. This bit cannot be accessed by an external device. It can be accessed only by the on-
15.4.11 HIF Bank Interrupt Control Register (HIFBICR)
HIFBICR is a 32-bit register that controls HIF bank interrupts. HIFBICR cannot be accessed by an
external device.
Bit
0
Bit
31 to 2
1
2. Writing 0 to this bit by the on-chip CPU is ignored.
Bit Name
DTRG
Bit Name
—
BIE
chip CPU.
Initial
Value
0
Initial
Value
All 0
0
R/W
R/W*
R/W
R*
R/W*
1
1
1
*
2
Description
HIFDREQ Trigger
When 1 is written to this bit, the HIFDREQ pin is
asserted according to the setting of the DMD and
DPOL bits in HIFSCR. This bit is automatically
cleared to 0 in synchronization with negate of the
HIFDREQ pin.
Though this bit can be set to 1 by the on-chip CPU, it
cannot be cleared to 0.
To avoid conflict between clearing of this bit by
negate of the HIFDREQ pin and setting of this bit by
the on-chip CPU, make sure this bit is cleared to 0
before setting this bit to 1 by the on-chip CPU.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Bank Interrupt Enable
Enables or disables a bank interrupt request (HIFBI)
issued to the on-chip CPU.
0: HIFBI disabled
1: HIFBI enabled
Rev. 6.00 Jun. 12, 2007 Page 407 of 610
Section 15 Host Interface (HIF)
REJ09B0131-0600