HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 313
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HD6417618
Manufacturer Part Number
HD6417618
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417618.pdf
(646 pages)
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12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR)
TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the transmission descriptor. Which transmission descriptor information is used
for processing by the E-DMAC can be recognized by monitoring addresses displayed in this
register. The address from which the E-DMAC is actually fetching a descriptor may be different
from the value read from this register.
12.2.18 Flow Control FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the
threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the
receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The
condition to start the flow control is decided by taking OR operation on the two thresholds.
Therefore, the flow control by the two thresholds is independently started.
When flow control is performed according to the RFD bits setting, if the setting is the same as the
depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when
the remaining FIFO is (FIFO data depth − 64) bytes. For instance, when RFD in FDR = 0 and
RFD in FCFTR = 0, flow control is started when (256 − 64) bytes of data is stored in the receive
FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR.
Bit
31 to 0
Bit
31 to 19
Bit Name
TDFA31 to
TDFA0
Bit Name
Initial
value
All 0
Initial
value
All 0
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R
R/W
R
R/W
These bits can only be read. Writing is prohibited.
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Transmission-Descriptor Fetch Address
Description
Rev. 6.00 Jun. 12, 2007 Page 281 of 610
REJ09B0131-0600
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