HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 448

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface (HIF)
Table 15.4 Consecutive Write Procedure to HIFRAM by External DMAC
Rev. 6.00 Jun. 12, 2007 Page 416 of 610
REJ09B0131-0600
No.
1
2
3
4
5
6
7
8
9
10
11
CPU
HIF initial setting
DMAC initial setting
Set HIFADR to
HIFRAM end address
− 8
Select HIFDATA and
write dummy data (4
bytes) to HIFDATA
Set HIFRAM
consecutive write with
address increment in
HIFMCR
Select HIFDATA and
write dummy data (4
bytes) to HIFDATA
External Device
→
DMAC
Activate DMAC
Consecutive
data write to
bank 1 in
HIFRAM
Write to end
address of bank
1 in HIFRAM
completes and
operation halts
Re-activate
DMAC
Consecutive
data write to
bank 0 in
HIFRAM
→ HIF bank
← Assert
→ HIF bank
← Assert
HIF
interrupt
occurs
HIFDREQ
interrupt
occurs
HIFDREQ
→ HIFRAM bank switching
← Set DTRG bit to 1
→ HIFRAM bank switching
← Set DTRG bit to 1
This LSI
CPU
HIF initial setting
by HIF bank interrupt
handler (external device
accesses bank 1 and on-
chip CPU accesses
bank 0)
by HIF bank interrupt
handler (external device
accesses bank 0 and on-
chip CPU accesses
bank 1)
Read data from bank 1 in
HIFRAM