HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 141

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
7.3
7.3.1
The architecture of this LSI has 32-bit address space. The upper three address bits divide the space
into areas P0 to P4, and the cache access methods can be specified for each area. For details, see
section 3, Cache. Each area indicated by the remaining 29 bits is divided into ten areas (five areas
are reserved) when address map 1 is selected or eight areas (three areas are reserved) when address
map 2 is selected. The address map is selected by the MAP bit in CMNCR. The BSC controls the
areas indicated by the 29 bits.
As listed in tables 7.2 and 7.3, memory can be connected directly to five physical areas of this LSI,
and the chip select signals (CS0, CS3, CS4, CS5B, and CS6B) are output for each area. CS0 is
asserted during area 0 access.
7.3.2
Areas 0, 3, 4, 5B, and 6B are divided by decoding physical address bits A28 to A25, which
correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of
area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space
is the address space in P1 to P3 areas obtained by adding to it H'20000000 × n (n = 1 to 6).
The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7
shadow spaces are reserved, so do not use it.
Abbreviation
IOIS16
DQMLU,
DQMLL
WAIT
MD5, MD3
*
Area Overview
Area Division
Shadow Area
As pins A25 to A16 act as general I/O ports immediately after a power-on reset, pull up
or pull down these pins outside the LSI as needed.
Input
Output Connected to the DQMxx pin when SDRAM is in use.
Input
Input
I/O
Function
PCMCIA 16-bit I/O Signal
Enabled only in little endian mode.
Drive this signal low in big endian mode.
DQMLU: Select signal for D15 to D8
DQMLL: Select signal for D7 to D0
External wait input
MD5: Selects data alignment (big endian or little endian)
MD3: Specifies area 0 bus width (8/16 bits)
Rev. 6.00 Jun. 12, 2007 Page 109 of 610
Section 7 Bus State Controller (BSC)
REJ09B0131-0600