HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 267

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.3.2
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD,
the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate
interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.
The interrupts generated due to this status register are indicated in the ECI bit in EESR.
Bit
0
Bit
31 to 5 
4
3
Bit Name
PSRTO

EtherC Status Register (ECSR)
Bit Name
PRM
Initial
Value
0
Initial
Value
All 0
0
0
R/W
R/W
R/W
R
R/W
R
Description
Promiscuous Mode
Setting this bit enables all Ethernet frames to be
received. All Ethernet frames means all receivable
frames, irrespective of differences or enabled/disabled
status (destination address, broadcast address,
multicast bit, etc.).
0: EtherC performs normal operation
1: EtherC performs promiscuous mode operation
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PAUSE Frame Retransfer Retry Over
Indicates that during the retransfer of PAUSE frames
when the flow control is enabled, the number of
retries has exceeded the upper limit set in the
automatic PAUSE frame retransfer count set register
(TPAUSER).
0: Number of PAUSE frame retransfers has not
1: Number of PAUSE frame retransfers has
Reserved
This bit is always read as 0. The write value should
always be 0.
exceeded the upper limit
exceeded the upper limit
Rev. 6.00 Jun. 12, 2007 Page 235 of 610
Section 11 Ethernet Controller (EtherC)
REJ09B0131-0600