HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 366

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.6
SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt
requests, and selects the transmit/receive clock source. The CPU can always read and write to
SCSCR. SCSCR is initialized to H'0000 by a power-on reset.
Rev. 6.00 Jun. 12, 2007 Page 334 of 610
REJ09B0131-0600
Bit
15 to 8
7
Serial Control Register (SCSCR)
Bit Name

TIE
Initial
value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI).
Serial transmit data in the transmit FIFO data register
(SCFTDR) is send to the transmit shift register
(SCTSR). Then, the TDFE flag in the serial status
register (SCFSR) is set to1 when the number of data in
SCFTDR becomes less than the number of
transmission triggers. At this time, a TXI is requested.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
1: Transmit-FIFO-data-empty interrupt request (TXI) is
Note: * The TXI interrupt request can be cleared by
disabled*
enabled
writing a greater number of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing the TDFE bit to 0
after reading 1 from the TDFE bit, or can be
cleared by clearing this bit to 0.