HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 521

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Register specifications
• Register specifications
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,
no user break occurs since instruction fetch is performed for an even address.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
 Channel A
 Channel B
Since instruction fetch is not a write cycle on channel A, a sequential condition does not
match. Therefore, no user break occurs.
Address: H'00027128, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
The ASID check is not included.
Address: H'00031415, Address mask: H'00000000
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
Address: H'00037226, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
Address: H'0003722E, Address mask: H'00000000
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Rev. 6.00 Jun. 12, 2007 Page 489 of 610
Section 18 User Break Controller (UBC)
REJ09B0131-0600