HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 243

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.2.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 9.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the
write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
Bit
2
1
0
Notes on Register Access
Bit Name
CKS2
CKS1
CKS0
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 2 to 0
These bits select the clock to be used for the
WTCNT count from the eight types obtainable by
dividing the peripheral clock (Pφ). The overflow
period that is shown inside the parenthesis in the
table is the value when the peripheral clock (Pφ) is
25 MHz.
000: Pφ (10 µs)
001: Pφ/4 (41 µs)
010: Pφ/16 (164 µs)
011: Pφ/32 (328 µs)
100: Pφ/64 (655 µs)
101: Pφ/256 (2.62 ms)
110: Pφ/1024 (10.49 ms)
111: Pφ/4096 (41.94 ms)
Note: If bits CKS2 to CKS0 are modified when the
WDT is operating, the up-count may not be
performed correctly. Ensure that these bits
are modified only when the WDT is not
operating.
Rev. 6.00 Jun. 12, 2007 Page 211 of 610
Section 9 Watchdog Timer (WDT)
REJ09B0131-0600