HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 295

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.3
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. When
the receive request bit is set, the E-DMAC reads the relevant receive descriptor. If the receive
descriptor active bit in the descriptor has the "active" setting, the E-DMAC prepares for a receive
request from the EtherC. When one receive buffer of data has been received, the E-DMAC reads
the next descriptor and prepares to receive the next frame. If the receive descriptor active bit in the
descriptor has the "inactive" setting, the RR bit is cleared and operation of the receive DMAC is
halted.
Note:
Bit
31 to 1
0
*
E-DMAC Receive Request Register (EDRRR)
Bit Name

RR
If the receive function is disabled during frame reception, write-back is not performed
successfully to the receive descriptor. Following pointers to read a receive descriptor
become abnormal and the E-DMAC cannot operate successfully. In this case, to make
the E-DMAC reception enabled again, execute a software reset by the SWR bit in
EDMR. To make the E-DMAC reception disabled without executing a software reset,
set the RE bit in ECMR. Next, after the E_DMAC has completed the reception and
write-back to the receive descriptor has been confirmed, disable the receive function of
this register.
Initial
value
All 0
0
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R
R/W
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Request
0: The receive function is disabled*
1: A receive descriptor is read and the E-DMAC is
Description
ready to receive
Rev. 6.00 Jun. 12, 2007 Page 263 of 610
REJ09B0131-0600