HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 210

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
Table 7.17 Access Address for SDRAM Mode Register Write
• Burst read/single write (burst length 1)
• Burst read/burst write (burst length 1)
Mode register setting timing is shown in figure 7.25. The PALL command (all bank precharge
command) is issued first. The REF command (auto-refreshing command) is then issued eight
times. The MRS command (mode register write command) is finally issued. Idle cycles, of which
number is specified by bits WTRP1 and WTRP0 in CSnWCR, are inserted between the PALL and
the first REF commands. Idle cycles, of which number is specified by bits WTRC1 and WTRC0
in CSnWCR, are inserted between the REF and REF commands, and between the 8th REF and
MRS commands. In addition, one or more idle cycles are inserted between the MRS and the next
command.
It is necessary to keep idle time of certain cycles for SDRAM before issuing the PALL command
after turning the power on. Refer the manual of the SDRAM for the idle time to be needed. When
the pulse width of the reset signal is longer then the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.
Rev. 6.00 Jun. 12, 2007 Page 178 of 610
REJ09B0131-0600
Data Bus Width
16 bits
Data Bus Width
16 bits
CAS Latency
2
3
CAS Latency
2
3
Access Address
H'F8FD5440
H'F8FD5460
Access Address
H'F8FD5040
H'F8FD5060
External Address Pin
H'0000440
H'0000460
External Address Pin
H'0000040
H'0000060