HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 12

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)................................................................... 81
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Section 7 Bus State Controller (BSC) ................................................................. 105
7.1
7.2
7.3
7.4
7.5
Rev. 6.00 Jun. 12, 2007 Page xii of xxxii
Features................................................................................................................................ 81
Input/Output Pins................................................................................................................. 83
Register Descriptions........................................................................................................... 83
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources.................................................................................................................. 95
6.4.1
6.4.2
6.4.3
6.4.4
Interrupt Exception Handling Vector Table......................................................................... 98
Interrupt Operation ............................................................................................................ 100
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 102
Features.............................................................................................................................. 105
Input/Output Pins............................................................................................................... 108
Area Overview................................................................................................................... 109
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions......................................................................................................... 113
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
Operation ........................................................................................................................... 141
7.5.1
7.5.2
7.5.3
Interrupt Control Register 0 (ICR0)........................................................................ 84
IRQ Control Register (IRQCR) .............................................................................. 85
IRQ Status register (IRQSR) .................................................................................. 88
Interrupt Priority Registers A to E (IPRA to IPRE)................................................ 93
External Interrupts .................................................................................................. 95
On-Chip Peripheral Module Interrupts ................................................................... 97
User Break Interrupt ............................................................................................... 97
H-UDI Interrupt ...................................................................................................... 97
Interrupt Sequence ................................................................................................ 100
Stack after Interrupt Exception Handling ............................................................. 102
Area Division........................................................................................................ 109
Shadow Area......................................................................................................... 109
Address Map......................................................................................................... 110
Area 0 Memory Type and Memory Bus Width .................................................... 112
Data Alignment..................................................................................................... 112
Common Control Register (CMNCR) .................................................................. 114
CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) ................... 115
CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) .................... 120
SDRAM Control Register (SDCR)....................................................................... 136
Refresh Timer Control/Status Register (RTCSR)................................................. 137
Refresh Timer Counter (RTCNT)......................................................................... 139
Refresh Time Constant Register (RTCOR) .......................................................... 140
Endian/Access Size and Data Alignment.............................................................. 141
Normal Space Interface ........................................................................................ 146
Access Wait Control ............................................................................................. 150