ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 146

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Counter Unit
Output Compare Unit
146
ATmega64(L)
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 62 shows a block diagram of the counter and its surroundings.
Figure 62. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or dec-
remented at each timer clock (clk
clock source, selected by the Clock Select bits (CS22:0). When no clock source is
selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed
by the CPU, regardless of whether clk
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR2). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the
Output Compare output OC2. For more details about advanced counting sequences
and waveform generation, see “Modes of Operation” on page 149.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation
selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will
set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 =
1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an
Output Compare interrupt. The OCF2 flag is automatically cleared when the interrupt is
executed. Alternatively, the OCF2 flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate
an output according to operating mode set by the WGM21:0 bits and Compare Output
mode (COM21:0) bits. The max and bottom signals are used by the Waveform Genera-
tor for handling the special cases of the extreme values in some modes of operation
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNTn
Increment or decrement TCNT2 by 1.
Select between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/counter clock, referred to as clk
Signalize that TCNT2 has reached maximum value.
Signalize that TCNT2 has reached minimum value (zero).
direction
count
clear
bottom
T2
Control Logic
). clk
T2
T2
is present or not. A CPU write overrides (has
can be generated from an external or internal
top
TOVn
(Int.Req.)
clk
Tn
T0
in the following.
Clock Select
( From Prescaler )
Detector
Edge
2490G–AVR–03/04
Tn