ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 307

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

SPI Serial Programming
Pin Mapping
SPI Serial Programming
Algorithm
2490G–AVR–03/04
Even though the SPI Programming interface re-uses the SPI I/O module, there is one
important difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI
I/O module are not used in the Programming interface. Instead, PE0 and PE1 are used
for data in SPI Programming mode as shown in Table 128.
Table 128. Pin Mapping SPI Serial Programming
Figure 147. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega64, data is clocked on the rising edge of SCK.
When reading data from the ATmega64, data is clocked on the falling edge of SCK. See
Figure 148 for timing details.
To program and verify the ATmega64 in the SPI Serial Programming mode, the follow-
ing sequence is recommended:
1. Power-up sequence:
Apply power between V
some systems, the programmer cannot guarantee that SCK is held low during
Power-up. In this case, RESET must be given a positive pulse of at least two
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
MISO (PDO)
MOSI (PDI)
Symbol
source to the XTAL1 pin.
SCK
CC
MOSI
MISO
SCK
and GND while RESET and SCK are set to “0”. In
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
PE0
PE1
PB1
PE0
PE1
PB1
XTAL1
RESET
GND
I/O
(1)
O
AVCC
I
I
VCC
+2.7 - 5.5V
+2.7 - 5.5V
(2)
ATmega64(L)
Serial Data Out
Serial Data In
Description
Serial Clock
ck
ck
≥ 12 MHz
≥ 12 MHz
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