ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 185

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Multi-processor
Communication Mode
2490G–AVR–03/04
Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2X = 0)
Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2X = 1)
The recommendations of the maximum receiver baud rate error was made under the
assumption that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The receiver’s system
clock (XTAL) will always have some minor instability over the supply voltage range and
the temperature range. When using a crystal to generate the system clock, this is rarely
a problem, but for a resonator the system clock may differ more than 2% depending of
the resonators tolerance. The second source for the error is more controllable. The baud
rate generator can not always do an exact division of the system frequency to get the
baud rate wanted. In this case an UBRR value that gives an acceptable low error can be
used if possible.
Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-
tering function of incoming frames received by the USART Receiver. Frames that do not
contain address information will be ignored and not put into the receive buffer. This
effectively reduces the number of incoming frames that has to be handled by the CPU,
in a system with multiple MCUs that communicate via the same serial bus. The Trans-
mitter is unaffected by the MPCM setting, but has to be used differently when it is a part
of a system utilizing the Multi-processor Communication mode.
If the Receiver is set up to receive frames that contain five to eight data bits, then the
first stop bit indicates if the frame contains data or address information. If the receiver is
set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying
address and data frames. When the frame type bit (the first stop or the ninth bit) is one,
the frame contains an address. When the frame type bit is zero the frame is a data
frame.
# (Data+Parity Bit)
# (Data+Parity Bit)
10
10
D
D
5
6
7
8
9
5
6
7
8
9
R
R
slow
slow
93.20
94.12
94.81
95.36
95.81
96.17
94.12
94.92
95.52
96.00
96.39
96.70
(%)
(%)
R
R
105.66
104.92
104.35
103.90
103.53
103.23
106.67
105.79
105.11
104.58
104.14
103.78
fast
fast
(%)
(%)
+5.66/-5.88
+4.92/-5.08
+4.35/-4.48
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
+5.79/-5.88
+5.11/-5.19
+4.58/-4.54
+4.14/-4.19
+3.78/-3.83
Max Total
Max Total
+6.67/-6.8
Error (%)
Error (%)
ATmega64(L)
Recommended Max
Recommended Max
Receiver Error (%)
Receiver Error (%)
±3.0
±2.5
±2.0
±2.0
±1.5
±1.5
±2.5
±2.0
±1.5
±1.5
±1.5
±1.0
185