ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 153

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Timing
Diagrams
2490G–AVR–03/04
between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 67 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without a Compare Match.
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set. Figure 68 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 68. Timer/Counter Timing Diagram, no Prescaling
Figure 69 shows the same timing data, but with the prescaler enabled.
TCNTn
(clk
TOVn
clk
clk
OCR2 changes its value from MAX, like in Figure 67. When the OCR2 value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match.
The timer starts counting from a higher value than the one in OCR2, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
I/O
Tn
/1)
MAX - 1
f
OCnPCPWM
MAX
=
----------------- -
N 510
f
clk_I/O
⋅
BOTTOM
ATmega64(L)
BOTTOM + 1
T2
) is therefore
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