ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 285

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Using the SPM Interrupt
Consideration While Updating
BLS
Prevent Reading the RWW
Section During Self-
programming
Setting the Boot Loader Lock
Bits by SPM
EEPROM Write Prevents
Writing to SPMCSR
2490G–AVR–03/04
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used
instead of polling the SPMCSR Register in software. When using the SPM interrupt, the
Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is
accessing the RWW section when it is blocked for reading. How to move the interrupts
is described in “Interrupts” on page 59.
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can
corrupt the entire Boot Loader, and further software updates might be impossible. If it is
not necessary to change the Boot Loader software itself, it is recommended to program
the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
During Self-programming (either Page Erase or Page Write), the RWW section is
always blocked for reading. The user software itself must prevent that this section is
addressed during the Self-programming operation. The RWWSB in the SPMCSR will be
set as long as the RWW section is busy. During Self-programming the Interrupt Vector
table should be moved to the BLS as described in “Interrupts” on page 59, or the inter-
rupts must be disabled. Before addressing the RWW section after the programming is
completed, the user software must clear the RWWSB by writing the RWWSRE. See
“Simple Assembly Code Example for a Boot Loader” on page 287 for an example.
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only
accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot
Loader section from any software update by the MCU.
See Table 109 and Table 110 for how the different settings of the Boot Loader Bits
affect the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock
bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”
when writing the Lock bits. When programming the Lock bits the entire Flash can be
read during the operation.
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
Bit
R0
7
1
6
1
BLB12
5
BLB11
4
BLB02
3
BLB01
2
ATmega64(L)
1
1
0
1
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