ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 43

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Oscillator
XTAL Divide Control Register
– XDIV
2490G–AVR–03/04
For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly between the pins. No external capacitors are needed. The
Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
clock source to TOSC1 is not recommended.
The XTAL Divide Control Register is used to divide the source clock frequency by a
number in the range 2 - 129. This feature can be used to decrease power consumption
when the requirement for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals
(clk
XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the
application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the
value of these bits is denoted d, the following formula defines the resulting CPU and
peripherals clock frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is
written to one, the value written simultaneously into XDIV6..XDIV0 is taken as the divi-
sion factor. When XDIVEN is written to zero, the value written simultaneously into
XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the
speed of all peripherals is reduced when a division factor is used.
Note:
Bit
Read/Write
Initial Value
I/O
, clk
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock
only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency
of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the
Timer/Counter0 registers may fail.
ADC
, clk
XDIVEN
R/W
7
0
CPU
, clk
XDIV6
R/W
FLASH
6
0
clk
) is divided by the factor defined by the setting of XDIV6 -
:
XDIV5
R/W
5
0
f
CLK
=
XDIV4
R/W
Source clock
--------------------------------- -
4
0
129 d
XDIV3
–
R/W
3
0
XDIV2
R/W
2
0
ATmega64(L)
XDIV1
R/W
1
0
XDIV0
R/W
0
0
XDIV
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