ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 222

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Slave Transmitter Mode
222
ATmega64(L)
In the Slave Transmitter mode, a number of data bytes are transmitted to a master
receiver (see Figure 102). All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
Figure 102. Data Transfer in Slave Transmitter Mode
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond
when addressed by a master. If the LSB is set, the TWI will respond to the general call
address (0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgment of the device’s own slave address or the general call
address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode
is entered. After its own slave address and the write bit have been received, the TWINT
flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in Table 91. The Slave Transmitter mode may also be entered if
arbitration is lost while the TWI is in the Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of
the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the master
receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not
addressed Slave mode, and will ignore the master if it continues the transfer. Thus the
master receiver receives all “1” as serial data. State 0xC8 is entered if the master
demands additional data bytes (by transmitting ACK), even though the slave has trans-
mitted the last byte (TWEA zero and expecting NACK from the master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the
Two-wire Serial Bus is still monitored and address recognition may resume at any time
by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the
TWI from the Two-wire Serial Bus.
SDA
SCL
TWCR
TWAR
Value
Value
TRANSMITTER
Device 1
SLAVE
TWINT
TWA6
0
Device 2
RECEIVER
MASTER
TWEA
TWA5
1
TWSTA
Device 3
TWA4
Device’s Own Slave Address
0
TWSTO
TWA3
0
........
TWWC
TWA2
Device n
0
V
CC
TWEN
TWA1
1
R1
TWA0
–
0
2490G–AVR–03/04
R2
TWGCE
TWIE
X