ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 258

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Boundary-scan Related
Register in I/O Memory
MCU Control and Status
Register – MCUCSR
Boundary-scan Chain
Scanning the Digital Port Pins Figure 127 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-
258
ATmega64(L)
The MCU Control and Status Register contains control bits for general MCU functions,
and provides information on which reset source caused an MCU Reset.
• Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling
or enabling of the JTAG interface, a timed sequence must be followed when changing
this bit: The application software must write this bit to the desired value twice within four
cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be
set to one. The reason for this is to avoid static current at the TDO pin in the JTAG
interface.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset,
or by writing a logic zero to the flag.
The Boundary-scan Chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having Off-chip connection.
tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn
– function, and a bi-directional pin cell that combines the three signals, Output Control –
OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.
The port and pin indexes are not used in the following description.
The Boundary-scan logic is not included in the figures in this Datasheet. Figure 128
shows a simple digital Port Pin as described in the section “I/O Ports” on page 64. The
Boundary-scan details from Figure 127 replaces the dashed box in Figure 128.
When no alternate port function is present, the Input Data – ID corresponds to the PINxn
Register value (but ID has no synchronizer), Output Data corresponds to the PORT
Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-
up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 128 to
make the scan chain read the actual pin value. For analog function, there is a direct con-
nection from the external pin to the analog circuit, and a scan chain is inserted on the
interface between the digital logic and the analog circuitry.
Bit
Read/Write
Initial Value
JTD
R/W
7
0
R
6
–
0
R
5
–
0
JTRF
R/W
4
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
1
PORF
R/W
0
2490G–AVR–03/04
MCUCSR