ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 354

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Changes from Rev.
2490B-09/02 to Rev.
2490C-09/02
Changes from Rev.
2490A-10/01 to Rev.
2490B-09/02
354
ATmega64(L)
10. Added section “EEPROM Write During Power-down Sleep Mode” on page 23.
11. Changed V
12. Added information about conversion time for Differential mode with Auto
13. Added t
14. Updated “Packaging Information” on page 349.
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad MLF Package and updated “Ordering Information” on page 348.
2. Added the section “Using all Locations of External Memory Smaller than 64
3. Added the section “Default Clock Source” on page 36.
4. Renamed SPMCR to SPMCSR in entire document.
5. Added Some Preliminary Test Limits and Characterization Data
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
7. Improved description on how to do a polarity check of the ADC diff results in
8. Updated Programming Figures:
9. Added a note regarding usage of the “PROG_PAGELOAD (0x6)” and
10. Updated “Two-wire Serial Interface” on page 196.
Triggering on page 234.
KB” on page 33.
Removed some of the TBD's and corrected data in the following tables and pages:
Table 2 on page 22, Table 7 on page 36, Table 9 on page 38, Table 10 on page 38,
Table 12 on page 39, Table 14 on page 40, Table 16 on page 41, Table 19 on page
50, Table 20 on page 54, Table 22 on page 56, “DC Characteristics” on page 326,
Table 132 on page 328, Table 135 on page 331, Table 137 on page 334, and Table
138 - Table 145.
See “Leaving Programming Mode” on page 322.
“ADC Conversion Result” on page 242.
Figure 138 on page 294 and Figure 147 on page 307 are updated to also reflect that
AVCC must be connected during Programming mode. Figure 142 on page 303
added to illustrate how to program the fuses.
“PROG_PAGEREAD (0x7)” instructions on page 314.
More details regarding use of the TWI Power-down operation and using the TWI as
master with low TWBRR values are added into the data sheet. Added the note at
the end of the “Bit Rate Generator Unit” on page 202. Added the description at the
end of “Address Match Unit” on page 203.
WD_FUSE
HYST
value to 120 in Table 19 on page 50.
in Table 129 on page 309.
2490G–AVR–03/04