ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 147

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Force Output Compare
Compare Match Blocking by
TCNT2 Write
2490G–AVR–03/04
(see “Modes of Operation” on page 149). Figure 63 shows a block diagram of the Output
Compare unit.
Figure 63. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR2 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double
buffering is disabled the CPU will access the OCR2 directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare
Match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be
updated as if a real Compare Match had occurred (the COM21:0 bits settings define
whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any Compare Match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when
the Timer/Counter clock is enabled.
bottom
FOCn
OCRn
top
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
ATmega64(L)
OCFn (Int.Req.)
OCn
147