ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 45

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Idle Mode
ADC Noise Reduction
Mode
Power-down Mode
Power-save Mode
2490G–AVR–03/04
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-
wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue
operating. This sleep mode basically halts clk
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-
rupts, the Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog
to continue operating (if enabled). This sleep mode basically halts clk
clk-
This improves the noise environment for the ADC, enabling higher resolution measure-
ments. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match inter-
rupt, a Timer/Counter0 interrupt, an SPM/EEPROM ready interrupt, an external level
interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU from ADC
Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external
interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue
operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a
Two-wire Serial Interface address match interrupt, an external level interrupt on INT7:4,
or an External Interrupt on INT3:0 can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Inter-
rupts” on page 88 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
36.
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously (i.e., the AS0 bit in ASSR is set),
Timer/Counter0 will run during sleep. The device can wake up from either Timer Over-
flow o r Ou tput Comp are event from Tim er/Coun ter0 if the corre sp ond ing
Timer/Counter0 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable
bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom-
mended instead of Power-save mode because the contents of the registers in the
FLASH
, while allowing the other clocks to run.
CPU
and clk
FLASH
ATmega64(L)
, while allowing the other
I/O
, clk
CPU
, and
45