R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 10

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
1.6 Functional Overview
1.6.1
1.6.2
1.6.2.1 External bus interface
1.6.2.2 FIFO buffer memory access method
1.6.2.3 FIFO buffer memory access method from DMAC
1.6.3
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below for the bus interface from the CPU. Access using a chip select pin (CS_N) and three strobe pins (RD_N, WR0_N
and WR1_N).
16-bit separate bus
16-bit multiplex bus
This controller is compatible with the following two access types as an access method of the FIFO buffer memory for
USB data transmission. Read (write) of the data from the FIFO buffer memory is possible by accessing (read/write) the
FIFO port from the CPU (DMAC).
(1) CPU access
(2) DMA access
USB communication is executed by a little endian. A byte endian swap function is provided in the FIFO port access.
For 16-bit access, the endian can be changed according to what is written to the register.
To access the FIFO buffer memory through the DMA access, select an access method from the following:
(1) Method of using common bus with CPU
(2) Method in which dedicated bus (split bus) is used
Selection of controller functions
Bus interface
The controller is compatible with the bus interfaces given below.
The CPU accesses the control register of the controller using the CPU bus interface. There are two types of access
Separate bus or multiplex bus are selected at the MPBUS pin signal level while canceling the hardware reset.
USB event
The controller notifies the events regarding USB operations to the user system through the interrupt. It also notifies that
the DMA interface can access the buffer memory of the selected pipe by asserting the DREQ signal. Depending on
what the software writes, interrupt notification activation can be selected for the type and factor.
The controller can toggle between Host functions and Peripheral functions according to what is written to the register.
The hardware can automatically identify the USB transmission speed, irrespective of whether the Host or Peripheral
function is selected.
Seven address buses (A7-1) and sixteen data buses (D15-0) are used.
The ALE pin (ALE) and sixteen data buses (D15-0) are used. The data bus uses the address and data in the time
division.
Write the data in, or read the data from, the FIFO buffer memory using the address signal and control signal.
Write the data in the FIFO buffer memory from the CPU’s built-in DMAC or dedicated DMAC, or read the data from
the FIFO buffer memory.
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