R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 114

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.1.10 State Transition Timing
3.1.10.1 Start of Internal Clock Supply (from H/W reset state to normal operating state)
3.1.10.2 Internal Clock Supply Stop (setup sequence to transition from normal operating state to low
–power sleep state)
R e v 1 . 0 1
Figure 3.2 shows a diagram of the clock supply start control timing for the controller. When transitioning from the H/W
reset state or the clock stopped state to the normal operating state, handle the bits according to the timing below.
Figure 3.3 shows the control timing diagram for transitioning the controller from the normal operating state to the
low-power sleep state. To enable the low-power sleep state, set “LPSME=1” in the initialization.
clock supply start
SCKE(H/W)
PLLC(H/W)
SCKE
XCKE
XCKE
PLLC
Start internal
(1) Enable oscillation buffer
(2) Software wait until “SCKE=1”. (Controller automatically enables PLLC and SCKE.)
(1) Confirm SOFCFG register EDGESTS bit, then use software wait until “EDGESTS=0”.
(2) Stop internal clock supply
(3) Software wait until internal clock stops. (requires 60ns or more wait)
(4) Stop PLL.
(5) Stop oscillation buffer operation
O c t 1 7 , 2 0 0 8
process
Start
Figure 3.3 Internal Clock Supply Stop Process Timing Diagram
(2)
Figure 3.2 Clock Supply Start Control Timing Diagram
p a g e 1 1 4 o f 1 8 3
(1)
(3) min 60ns
(4)
“XCKE=1”
“XCKE=0”
“SCKE=0”
“PLLC=0”
(5)
(2)