R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 2

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.2.10 Other functions
R e v 1 . 0 1
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Compatible with all USB transfer types
Bus interface
Pipe configuration
Features when selecting Host functions
Features when selecting Peripheral functions
Functions that Provide On-The-Go Support
Control transfer
Bulk transfer
Interrupt transfer (not compatible with high-bandwidth)
Isochronous transfer (not compatible with high-bandwidth)
Pipe0: Control transfer, single buffer fixed at 256 bytes
Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes.
Pipe3~Pipe5: Bulk transfer, continuous transfer modes,
Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes
Compatible with all USB transfer types, including isochronous transfer
16-bit CPU bus interface
8-bit split bus (exclusive for external direct memory access controller (DMAC)) interface
Built-in two DMA interface channels
DMA transfer provides 40MB/second high-performance data transfer
Built-in 8.5KB buffer memory for USB communication
Maximum of ten pipes can be selected (including default control pipe)
Programmable pipe configuration
Any endpoint address can be assigned to Pipe1 to Pipe9
Transfer conditions that can be written for each pipe
Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps)
Several Peripheral devices can be connected through one tier hub
Reset handshake auto response
SOF and packet transmission schedule automation
Transfer interval setup function for Isochronous and Interrupt transfer
Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps)
Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response
Control transfer stage management function
Device state management function
Auto response function related to SET_ADDRESS request
NAK response interrupt function (NRDY)
SOF interpolation function
Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up
Built-in control bit facilitates Host Negotiation Protocol
Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function
Transfer end function according to transaction count
End function of DMA transfer by external trigger (DEND pin)
SOF plus output function
Three types of input clock can be selected by built-in PLL
Function to modify the BRDY interrupt event notification timing (BFRE)
Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM)
Function to provide the auto clock from clock stop status
NAK setting function (SHTNAK) for PID response corresponding to transfer end
Compatible with 16-bit separate bus/16-bit multiplex bus
Compatible with DMA transfer in 8-bit/16-bit access (slave function)
Select from 48MHz/24MHz/12MHz
O c t 1 7 , 2 0 0 8
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
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