R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 37

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
R e v 1 . 0 1
DMA signal control
If transferring data using the DMA interface, use the DMAxCFG register’s BURST bit, PKTM bit, DENDE bit, and
OBUS bit to select the DMA interface operation (assert/negate of DREQx_N /DENDx_N signal and DMA transfer
mode settings) that is configured to the user
the pipe selected by the DxFIFOSEL register CURPIPE bit (to be mentioned later). When the status of the pipe FIFO
buffer changes to buffer ready (BRDY) status, this controller asserts the DREQx_N signal if "DREQE=1".
DREQx_N signal polarity selection bit (DREQA)
Set active of DREQx_N pin in this bit.
For the FIFO port, write to this bit when "CURPIPE=000".
Burst mode bit (BURST)
When the DMA controller executes a cycle steal transfer for DxFIFO, write "0" to this bit. The controller negates a
DREQx_N signal for access to one word or one byte.
When the DMA controller executes a burst transfer for DxFIFO, write "1" to this bit. The controller negates the
DREQx_N signal for accessing the last one word or one byte of FIFO buffer.
Do not modify the bit during pipe communication operations.
DACKx_N signal polarity selection bit (DACKA)
In this bit, set active the DACKx_N pin.
For the FIFO port, write to this bit when "CURPIPE=000".
DMA transfer signal selection bit (DFORM)
In this bit, set the control signal while accessing the FIFO buffer with the DMA controller.
For the FIFO port, write to this bit when "CURPIPE=000"
DENDx_N signal polarity selection bit (DENDA)
In this bit, set active the DENDx_N pin.
For the FIFO port, write to this bit when "CURPIPE=000".
DEND output packet mode bit (PKTM)
Write the DEND output timing in this bit.
When "0" is written to this bit, the controller asserts the DENDx_N signal when any of the following conditions are
fulfilled:
(1) During the last read access while reading the short packet data
(2) During the last read access while reading the data completed at the transaction counter (TRNCNT)
(3) If a zero-length packet is received when the FIFO buffer is empty
When "1" is written to this bit, the controller asserts a DENDx_N output for every data transfer of the given FIFO buffer
size.
For the FIFO port, write to this bit when "CURPIPE=000".
O c t 1 7 , 2 0 0 8
p a g e 3 7 o f 1 8 3
system.
The DMA signal is valid for access to the FIFO buffer assigned to