R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 109

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.1.4
3.1.5
3.1.6
3.1.6.1 When Host Controller function is selected
3.1.6.2 When Peripheral Controller Function is selected
R e v 1 . 0 1
USB Block Operation Enable
Controller Function Selection Bit Setting
Hi-Speed Operation Enable Bit Setting and USB Transmission Speed Determination
After clock supply has started to the USB block (“SCKE = 1”), set the SYSCFG register USBE bit to “1" with software
to enable USB block operations.
After enabling the USB block operations, set the controller function selection bit (SYSCFG register DCFM bit).
Table 3.4 shows the function selections for each USB port on the controller.
When the Host Controller function is selected, set the Hi-Speed operation enable bit (PORT0: SYSCFG register HSE
bit, PORT1: SYSCFG1 register HSE bit) to “1” only after attachment of Peripheral device is detected and the D+ line of
the attached device is pulled up (i.e. not in Low-Speed mode). If the attached device is Low-Speed, or if Hi-Speed
operation is not enabled, set the Hi-Speed operation enable bit of the corresponding PORT to “0”.
In addition, if the attached device is Low-Speed, the SOFCFG register TRNENSEL bit must be set to “1”. See Chapter
3.6.1 for more details.
When a USB reset is issued (“USBRST = 1”) to a PORT which is enabled for Hi-Speed operation, the controller will
execute the Reset Handshake Protocol and automatically determine the USB transmission speed. The result of the
PORT0 Reset Handshake is displayed in the DVSTCTR1 register RHST bit and the PORT1 result in DVSTCTR1
register RHST bit.
When the Peripheral Controller function is selected and Hi-Speed operation is enabled, set the Hi-Speed operation
enable bit (SYSCFG register HSE bit) to “1” after setting the controller function selection bit.
If operating the controller only at Full-Speed, set the SYSCFG register HSE bit to“0”.
When Hi-Speed operation is enabled, the controller executes the reset handshake protocol and automatically
determines the USB transmission speed. The result of the reset handshake is shown in the DVSTCTR0 register RHST
bit.
Use software to select either the Host Controller function or the Peripheral Controller function.
When Host Controller function is selected (“DCFM = 1”)
When Peripheral Controller function is selected (“DCFM = 0”)
No.
(1)
(2)
(3)
(4)
(5)
O c t 1 7 , 2 0 0 8
Full or Low
Full or Low
Hi-Speed
Hi-Speed
Hi or Full
PORT0
PORT0
p a g e 1 0 9 o f 1 8 3
Full or Low
Full or Low
Table 3.4 USB Port Function Selections
Hi-Speed
Hi-Speed
PORT1
PORT1
unused
Transfer scheduling is shared between PORT0 and PORT1
and the output is driven to both ports.
Transfer scheduling is operated separately for
PORT0/PORT1 and is not dependent on the transfer speed
of each port.
PORT1 is invalid. Low-Speed is not supported.
Scheduling for each port
Notes