R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 137

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.4.2
3.4.2.1 FIFO Port Selection
3.4.2.2 REW Bit
R e v 1 . 0 1
FIFO Port Function
This section describes the FIFO port functions. Table 3.15 shows definitions of the FIFO port function settings for the
controller. When data write access is enabled and data is written up to buffer full state (in non-continuous transfer:
maximum packet size), the port automatically goes to the USB bus send enabled status. To enable data send of less
than buffer full (in non-continuous transfer: less than number of maximum packet size), the port must be set to write
complete in the C/DxFIFOCTR register BVAL bit (DMA transfer: DEND signal). To send a zero-length packet, the port
must be set to write complete in the BVAL bit in addition to clearing the buffer with the BCLR bit of the same register.
When a read access is executed, if all the data is read, the port automatically goes to the new packet receive enable
status. However, when a zero-length packet is received (DTLN=0), the data cannot be read and the buffer must be
cleared in the BCLR bit of the same register. The receive data length is confirmed in the C/DxFIFOCTR register DTLN
bit.
Table 3.16 shows the list of pipes that can be selected in each FIFO port. The pipes to be accessed are selected with
the C/DxFIFOSEL register CURPIPE bit. After selecting the pipes, confirm that the CURPIPE value written was read
correctly (if the previous pipe number is read out, this indicates the controller is still processing the pipe change), then
confirm that “FRDY=1” and access the FIFO port.
Also, select the bus width for the FIFO port access with the MBW bit.
The buffer memory access direction is determined by the ISEL bit for DCP, and the PIPExCFG register DIR bit for all
other pipes.
The REW bit the C/DxFIFOSEL register in allows the user to temporarily stop the current pipe access, execute access
of another pipe, then continue the current pipe access process again.
C/DxFIFOSEL
C/DxFIFOCTR
External pin
Register Bit
O c t 1 7 , 2 0 0 8
DCP
PIPE 1-7
PIPE
RCNT
REW
DCLRM
DREQE
MBW
BIGEND
ISEL
CURPIPE
BVAL
BCLR
FRDY
DTLN
DEND
Bit Name
p a g e 1 3 7 o f 1 8 3
CPU access
CPU access
DMA access
Table 3.15 FIFO Port Function Settings
Table 3.16 FIFO Port Access by PIPE
Selects DTLN read mode
Buffer memory window (re-read, re-write)
Automatically clears buffer memory after specified
pipe received date is read
DREQ signal assert
FIFO port access bit width
FIFO port endian control
FIFO port access direction
Selects Current PIPE
Buffer memory write end
Clears CPU-side buffer memory
Monitors FIFO port ready
Confirms received data length
Buffer memory write end
Access Method
Function
CFIFO port register
CFIFO port register
DxFIFO port register
DxFIFO port register
Usable Ports
2.8.4
3.4.2.2
2.8.11
3.4.1.2
3.4.3.4
3.4.3
2.8.5
3.4.2.1
2.8.6
2.8.7
3.4.2.1
2.8.8
2.8.16
2.8.17
3.4.1.2
2.8.18
2.8.19
0
3.4.3.3
Refernece
DxFIFO only
DxFIFO only
DCP only
DMA transfer
only
Notes