R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 54

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
Remarks
* To clear the status indicated by the VBINT, RESM, SOFR, DVST or CTRT bits, write "0" only for the bit to be cleared, and
write "1" for other bits. Do not write "0" to the status bit set to "0".
* The controller detects the change in status indicated by the VBINT and RESM bits of this register, even while the clock is
being stopped ("SCKE=0"), and notifies the interrupt if the corresponding interrupt is enabled. When the clock is enabled, clear
the status using software.
* The statuses of the RESM, DVST and CTRT bits change only when the Peripheral Controller function is selected. When the
Host Controller function is selected, write "0" to the corresponding interrupt enabled bit in order to disablethe the interrupt.
* The DVSQ, VALID and CTRQ bits are valid only when the Peripheral Controller function is selected.
2.11.1 VBUS conversion interrupt status bit (VBINT)
2.11.2 Resume interrupt status bit (RESM)
2.11.3 Frame number update interrupt status bit (SOFR)
2.11.3.1 When the Host Controller function is set
2.11.3.2 When the Peripheral Controller function is set
2.11.4 Device state transition interrupt status bit (DVST)
R e v 1 . 0 1
2-0
Bit
CTSQ
Control transfer stage
When the controller detects the change in the VBUS pin input value (from High to Low and from Low to High), "1" is
written to this bit. The controller writes the input value of the VBUS pin to the VBSTS bit. When the VBINT interrupt
occurs, use the software to execute a consistency check several times during the VBSTS bit read, and reject the
chattering.
When writing to the Peripheral Controller function, the controller is in suspend status (DVSQ=1XX), and "1" is set to
this bit when the DP pin falling edge is detected.
The conditions when the controller sets "1" in this bit are below.
While updating the frame number, the controller sets "1" to this bit (this interrupt is detected every 1ms). The controller
detects the SOFR interrupt by internal interpolation even if the SOF packet from the USB Host is corrupted.
When the Peripheral Controller function is set, if the controller detects a change in the device state, it updates the
DVSQ value and sets "1" to this bit.
When this interrupt occurs, clear the status before the controller detects the next device status state transition.
This controller sets "1" for this bit in the condition where at least one of the UACT bits corresponding to Port0 or Port1
writes "1" by the software, during the timing when the frame number is updated (this interrupt is detected every 1ms).
O c t 1 7 , 2 0 0 8
Name
p a g e 5 4 o f 1 8 3
Control transfer stage is set.
000: Idle or Setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (no data) status stage
110: Control transfer sequence error
111: Reserved
Function
Software Hardware Remarks
R
W
when H)
invalid
(Read
value
P