R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 132

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.4 Buffer Memory
3.4.1
R e v 1 . 0 1
Buffer Memory Allocation
This section describes operations concerning the controller’s built-in buffer memory. Unless specified, the operations
apply to both Host and Peripheral function selections.
Figure 3.14 provides an example buffer memory map of the controller. The buffer memory is an area shared by the
CPU that controls the user system and this controller. The various buffer memory conditions determine access
authority for the user system (CPU side) and/or this controller (SIE side).
The buffer memory is set into independent areas for each pipe. The memory area is set in 64-byte blocks by the block
start addresses and the number of blocks (set in PIPEBUF register BUFNMB bit and BUFSIZE bit). When selecting
the continuous transfer mode with the PIPExCFG register CNTMD bit, make sure the BUFSIZE bit is set in integral
multiples of the maximum packet size. Also, when selecting the double buffer in the PIPExCFG register DBLB bit, 2
areas of the memory specified in the PIPEBUF register BUFSIZE bit will be allocated for the corresponding pipe.
Three FIFO ports are used for access (data read/write) to the buffer memory. The pipe number of the pipe assigned to
each FIFO port is specified in the C/DxFIFOSEL register CURPIPE bit.
The buffer status (enable/disable access for data read/write to buffer memory from CPU) of each pipe can be
confirmed in the BSTS and INBUFM bits of the DCPCTR and the PIPExCTR registers. Also, FIFO port access
authorization can be confirmed in the C/DxFIFOCTR register FRDY bit.
O c t 1 7 , 2 0 0 8
p a g e 1 3 2 o f 1 8 3