R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 55

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.11.5 Control transfer and stage transition interrupt status bit (CTRT)
2.11.6 Buffer empty interrupt status bit (BEMP)
2.11.7 Buffer not ready interrupt status bit (NRDY)
2.11.8 Buffer ready interrupt status bit (BRDY)
R e v 1 . 0 1
The controller sets "1’ in the interrupt when, among the BEMPSTS register PIPEBEMP bits corresponding to the pipe
for which "1" is written to the BEMPENB register PIPEBEMPE bit (when the controller detects the BEMP interrupt
status for at least one pipe from the pipes for which the software has enabled the BEMP interrupt notification), at least
one bit is "1".
Refer to the PIPEBEMP register for assert conditions of the PIPEBEMP status.
If the software writes "0" for all the PIPEBEMP bits corresponding to the pipe that is enabled by the PIPEBEMPE bit,
the controller clears this bit to "0’. This bit cannot be cleared to "0" even if "0" is written to this bit by the software.
The controller sets "1" in the interrupt when, among the BNRDYSTS register PIPENRDY bits corresponding to the pipe
for which "1" is written to the NRDYENB register PIPENRDYE bit (when the controller detects the NRDY interrupt
status for at least one pipe from the pipes for which the software has enabled the NRDY interrupt notification), at least
one bit is "1".
Refer to the PIPENRDY register for assert conditions of the PIPENRDY status.
If the software writes "0" to all the PIPENRDY bits corresponding to the pipe that is enabled by the PIPENRDYE bit, the
controller clears this bit to "0". This bit cannot be cleared to "0’ even if the software writes "0" to this bit.
The controller sets "1" in the interrupt when, among the BRDYSTS register PIPEBRDY bits corresponding to the pipe
for which "1" is written in the BRDYENB register PIPEBRDYE bit (when the controller detects the BRDY interrupt
status for at least one pipe from the pipes for which the software has enabled the BRDY interrupt notification), at least
one bit is "1".
Refer to the PIPEBRDY register for the assert conditions of the PIPEBRDY status.
If the software writes "0" to all the PIPEBRDY bits corresponding to the pipe that is enabled by the PIPEBRDYE bit, the
controller clears this bit to "0". This bit cannot be cleared to "0" even if the software writes "0" to this bit.
When writing the Peripheral Controller function, if the controller detects the stage transition of control transfer, it
updates the CTSQ value and sets "1" to this bit.
When this interrupt occurs, clear the status before the controller detects stage transition after the control transfer.
O c t 1 7 , 2 0 0 8
p a g e 5 5 o f 1 8 3