R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 143

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.5 Data Setup Timing
R e v 1 . 0 1
the bus with another device, ”OBUS=1” shall be set.
to be used as mid-rail voltage.
*1)
Direction
DREQ
DACK
SD7-0
DEND
When ”OBUS=0” is set in the read direction, SD0-7/DEND signal are always output. Note that, therefore, when sharing
When ”OBUS=0” is set in the write direction, SD0-7/DEND signals are always input-enabled. Do not allow the signals
This section describes the OBUS bit that sets the split bus timing. The same operations apply in both Host and
Peripheral Function selections.
The timing of the SD0-7 and DEND pins can be modified through the DMAxCFG register OBUS bit as described in
Table 3.21. The OBUS bit function is only valid for DMA transfers using a split bus. When using the CPU bus for DMA
transfers, the OBUS bit setting is ignored.
Figure 3.19 shows the configuration of data setup timing by the OBUS bit.
Read
Write
The control signal indicates DACKx_N when DMAxCFG register DFORM [9 – 7] is “100”.
O c t 1 7 , 2 0 0 8
Bit Setting
Table 3.21 Operation Differences According to OBUS Bit Setup Value
OBUS
0
1
0
1
OBUS=1: normal mode
p a g e 1 4 3 o f 1 8 3
SD0-7/DEND signals are output normally, regardless of the control signal *1.
If the control signal is negated, the next data is output.
Therefore, the DMAC data setup timing is secured and Hi-Speed DMA transfer is enabled.
SD0-7/DEND signals are output after the control signal is asserted.
SD0-7/DEND signals go to Hi-z if the control signal is negated.
SD0-7/DEND signals are output normally, regardless of the DACKx_N signal.
The DMAC can output the next data before the DACKx_N signal is asserted.
Therefore, the controller data setup timing is secured and Hi-Speed DMA transfer is
enabled.
SD0-7/DEND signals are input-enabled only when the DACKx_N signal is asserted.
SD0-7/DEND signals are ignored if the DACKx_N signal is negated.
Figure 3.19 Data Setup Timing Configuration
Operation
OBUS=0: High-Speed mode