R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 169

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
4.11 Timing Diagram
4.11.1 CPU access timing (when a separate bus is set)
4.11.1.1 CPU access write timing (when a separate bus is set)
4.11.1.2 CPU access read timing (when a separate bus is set)
Note 1-1: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N.
Note 1-2: The control signal, when reading data, is a combination of CS_N and RD_N.
Note 1-3: RD_N, WR0_N, and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to
fall when RD_N or WR0_N, and WR1_N are rising. In the above instances, an interval of at least 10ns must be left open.
R e v 1 . 0 1
WR1_N,
WR0_N
D15-D0
A6-A1
CS_N
O c t 1 7 , 2 0 0 8
D15-D0
A6-A1
CS_N
Note 1-3
Note 1-2
RD_N
Note 1-3
Note1-1
31
tsur(A)
5
p a g e 1 6 9 o f 1 8 3
ten(CTRL-D)
3
ta(A)
ta(CTRL-D)
1
Address determination
Address determination
tsuw(A)
39
tw(CTRL)
twr(CTRL)
30
42
thr(A)
Data determination
47-1
47-1
Data determination
34
tsu(D)
tw(cycle1)
tw(cycle1)
43
tv(CTRL-D)
trec(CTRL),
th(D)
trec(CTRL),
tdis(CTRL-D)
thw(A)
4
33
40
44
tv(A)
40
trecr(CTRL)
2
6
trecr(CTRL)
41
41