R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 60

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.11.16 Port1 OVRCR interrupt status bit (OVRCR)
2.11.17 Port1 USB bus change interrupt status bit (BCHG)
2.11.18 Port1 USB detach detection interrupt status bit for the Host Controller function (DTCH)
2.11.19 Port1 USB attach detection interrupt status bit for the Host Controller function (ATTCH)
2.11.20 Port1 EOF error interrupt status bit for the Host Controller function (EOFERR)
R e v 1 . 0 1
When input status of the OVCUR1 pin is modified (from High to Low, or from Low to High), this controller detects the
Port1 OVRCR interrupt and setss "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by
the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller shows the
present status of the OVCUR1 pin in the SYSSTS1 register OVCMON bit.
When selecting the Host Controller function, it is possible to detect the software over-current occurrence if the
over-current notification signal from the power supply IC that supplies to the VBUS for the devices to be connected to
the USB on Port1 is set to the OVCUR1 pin. When the OVRCR interrupt is issued, use the software to check the
consistency in reading of OVCMON bit several times and reject the chattering.
When selecting the Host Controller function, and when this controller detects the J-State or K-State of the
Full-/Low-Speed signal level on Port0 within 2.5µs, this controller detects the Port1 ATTCH interrupt and sets "1" to this
bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the
INT_N pin and notifies that the interrupt is issued. Refer to 2.11.12.
When this controller detects that the communication for Port1 is not closed at the point of EOF2 timing as defined in the
USB Specification Revision 2.0, this controller detects the Port1 EOFERR interrupt and sets "1" to this bit. Here, if "1"
has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and
notifies that the interrupt is issued. Refer to 2.11.13.
When a state change for the Port1 Full-/Low-Speed signal level is issued (from J-State, K-State, or SE0 State to
J-State, K-State or SE0 State), this controller detects the Port1 BCHG interrupts and sets "1" to this bit. Here, if "1" has
been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies
that the interrupt is issued. This controller displays the present input status of Port0 in the SYSSTS1 register LNST bit.
Refer to
When the USB bus detach for Port1 is detected, this controller detects the Port1 DTCH interrupt and sets "1" to this bit.
Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N
pin and notifies that the interrupt is issued. Refer to 2.11.11.
O c t 1 7 , 2 0 0 8
2.11.10.
p a g e 6 0 o f 1 8 3