R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 108

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3 Operating Instructions
3.1 System Controls and Oscillation Controls
3.1.1
3.1.2
3.1.3
R e v 1 . 0 1
This chapter provides instructions concerning register operations necessary to initialize the R8A66597 controller and
descriptions of the registers necessary to control power consumption.
x = 0 or 1
RESET
Bus Interface Setting
Clock Supply Control
Table 3.1 shows the list of the various resets related to this controller. Please refer to “Chapter 2. Registers” for a
description of the register initialization status after each reset operation.
Table 3.2 shows the parameters for the controller bus interface that must be set before enabling (“XCKE = 0”) the
oscillation buffer operation. Make sure these are set immediately after the H/W reset. Table 3.3 shows the parameters
to be set after the oscillation buffer operation is enabled (“XCKE = 1” is set and controller is in “SCKE = 1” status).
The clock supply to the controller USB block is started by selecting the XIN pin input clock in the SYSCFG register
XTAL bit and enabling the oscillation buffer in the XCKE bit by software.
Confirm by software that the SCKE bit is set to “1”, then proceed with the next process.
O c t 1 7 , 2 0 0 8
PINCFG
PINCFG
SYSCFG1
SYSCFG1
DMAxCFG
DMAxCFG
DMAxCFG
DMAxCFG
SOFCFG
SOFCFG
Register Name
Register Name
H/W Reset
USB Bus Reset
Table 3.2 Bus Interface Settings (set before clock supply starts)
Table 3.3 Bus Interface Settings (set after clock supply starts)
Name
p a g e 1 0 8 o f 1 8 3
LPSME
DACKA
DENDA
LDRV
INTA
PCSDIS
DREQA
OBUS
BRDYM
INTL
Bit Name
Bit Name
”L” level input from RST_N pin
When Peripheral Controller function is selected, controller
detects reset automatically from D+/D- line status
Specify drive current controls
Set INT_N pin polarity
Specify include/exclude CS_N assert in recovery conditions
from low power sleep state
Specify enable/disable for low power sleep state
Set DREQx_N pin polarity
Set DACKx_N pin polarity
Set DENDx_N pin polarity
Set OBUS mode
Set PIPEBRDY interrupt status clear timing
Set INT_N pin output sense
Table 3.1 RESET List
Operation
Setting Description
Setting Description