R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 144

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.6 Control Transfer (DCP)
3.6.1
3.6.1.1 Setup Stage
3.6.1.2 Data Stage
3.6.1.3 Status Stage
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Control Transfer with Host Controller Function
Data transfer in the data stage of the control transfer uses the default control pipe (DCP). The DCP buffer memory is a
256-byte single buffer fixed area used for both control read and control write events. Only the CFIFO port is enabled
for access to the buffer memory.
Stage transition is managed for control transfers by software in the following manner.
When the Peripheral Device corresponding to the control transfer is in Low-Speed operation, set the SOFCFG register
TRNENSEL bit to “1” for the control transfer period with the device.
The following registers are used for USB request send events in the setup transaction: USBREQ , USBVAL , USBINDX ,
and USBLENG . By writing a setup packet data to the registers and setting “1” in the DCPCTR register SUREQ bit “1”,
the set data will be sent as the setup transaction. The SUREQ bit is written to “0” by H/W after the transaction is
completed. Do not use the above-listed USB request registers while “SUREQ=1”.
After Peripheral Device attachment is detected, issue the initial setup transaction for the device by setting the
DCPMAXP register DEVSEL bit to “0” and setting the DEVADD0 register UPPHUB, HUBPORT , USBSPD , and
RTPORT bits as described in the sequence above.
After the Peripheral device has transitioned to the Address state, issue the setup transaction in the above-described
sequence after setting the assigned USB Address value to the DEVSEL bit and setting each bit of the DEVADDx
register that corresponds to the USB Address. For example when “DEVSEL=0x2”, set the DEVADD2 register; when
“DEVSEL=0xA”, set the DEVADDA register.
After the transaction is sent, an interrupt request is issued in response from the peripheral ( INTSTS1 register SIGN bit
and SACK bit). The setup transaction result can be confirmed by this interrupt request.
The setup transaction data packet is always the DATA0 data packet (USB request), regardless of the contents of the
DCPCTR register SQMON bit.
The data stage uses the DCP buffer memory for data transfers.
To access the DCP buffer memory, set the access direction in the CFIFOSEL register ISEL bit. Also set the transfer
direction in the DCPCFG register DIR bit.
The first packet in the data stage must transmit the data PID as DATA1. Execute the transaction by setting the data
PID as DATA1 in the DCPCFG register SQSET bit and setting the PID bit to BUF. Data transfer completion is detected
by the BRDY or BEMP interrupts.
In control write transfers, when the send data is in integral multiples of the maximum packet size, use software to
output a zero-length packet as the last packet.
For transmissions in the data send direction in Hi-Speed operations, the user can select PING or OUT for the first
token to be issued by setting the DCPCTR register PINGE bit.
PING packet control is the same as that for bulk transfers. Refer to 3.7.1 for more details.
The status stage transfers data in a zero-length packet in the opposite direction of the data stage. As in the data stage,
the DCP buffer memory is used for data transfers. Transactions are executed in the same procedure as that of the
data stage.
The status stage data packet must transmit the data PID as DATA1. Make sure data PID is set as DATA1 in the
DCPCFG register SQSET bit.
Also, for zero-length packet receive events, confirm the received data length in the CFIFOCTR register DTLN bit after
the BRDY interrupt is generated, then clear the buffer memory with the BCLR bit.
For transmissions in the data send direction in Hi-Speed operation, the user can select PING or OUT for the first token
to be issued by setting the DCPCTR register PINGE bit.
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