R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 142

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.4.4
3.4.4.1 FIFO Port Access Enable Timing at Pipe Switch
3.4.4.2 FIFO Port Access Enable Timing after Double Buffer Read/Write is Completed
R e v 1 . 0 1
Figure 3.18 Figure 3.18 FRDY, DTLN Confirmation Timing after Double Buffer Read/Write Complete
WR_N /
CURPIPE
FRDY
DTLN
WR N
CURPIPE
FRDY
DTLN
FIFO Port Access Enable Timing
This section describes the FIFO port access enable timing.
Figure 3.17 shows the timing diagram up to confirmation of the FRDY and DRLN bits when the pipe specified by the
FIFO port is switched (modified C/DxFIFOSEL register CURPIPE bit).
When the CURPIPE bit is modified, first confirm that the written CURPIPE value was read correctly (if the previous
pipe number is read out, this indicates the controller is still processing the pipe modification), then confirm that
“FRDY=1” and access the FIFO port.
The same timing applies to modification of the ISEL bit for the CFIFO port.
Figure 3.18 shows the timing diagram up to when access is enabled for the second buffer, after the buffer read or write
is completed in the double buffer mode.
In the double buffer mode, always access the FIFO port after waiting 300ns after the access just before the toggle.
The same timing is applied to sending a short packet by setting “BVAL=1” in the IN direction pipe.
RD_N
O c t 1 7 , 2 0 0 8
Access just before buffer toggle
Buffer-A
Buffer-A
PIPE-A
PIPE-A
PIPE-A
Write to CURPIPE bit
p a g e 1 4 2 o f 1 8 3
Figure 3.17 FRDY, DRLN Fix Timing after Pipe Switch
min 20ns
min 20ns
max 100ns
Undetermined
PIPE-A
max 300ns
Undetermined
Undetermined
PIPE-B
max 450ns
Buffer-B
Buffer-B
PIPE-B
PIPE-B