R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 6

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
1.4 Pin Description
R e v 1 . 0 1
SOF output
SPLIT bus
DMA bus
CPU bus
Interrupt/
interface
interface
interface
System
control
Clock
Pin descriptions are given in Table 1.1, and the processing method of unused pins is given in Table 1.2.
O c t 1 7 , 2 0 0 8
DREQ0_N
DREQ1_N
DEND0_N
DEND1_N
DACK0_N
DACK1_N
Pin Name
USB bus
interface
MPBUS
WR0_N
WR1_N
SOF_N
AD7-1
SD7-0
INT_N
D15-0
RD_N
XOUT
CS_N
A7-1
ALE
XIN
D15-8 byte write
acknowledgeme
D7-0 Byte write
Address latch
Split data bus
DMA request
DMA transfer
Address bus
address bus
Read strobe
Reset signal
Chip select
SOF pluse
P a g e 6 o f 1 8 3
Bus mode
Output for
oscillation
oscillation
Data bus
Multiplex
selection
Interrupt
Input for
enabled
strobe
strobe
output
Name
DMA
end
nt
OUT
OUT
OUT
OUT
I/O
I/O
I/O
I/O This is a 16-bit data bus.
I/O
IN
IN
IN The controller is selected in "L" level.
IN
IN
IN
IN
IN
IN
IN Resets this controller at "L" level.
Table 1.1 Pin Description
When selecting to the multiplex bus, these pins
are used in the time division as a part of the
data bus (D7-D1) or address bus (A7-A1).
This is the address bus.
A0 does not exist for the 16-bit data bus.
While selecting to the multiplex bus, the A7 pin
is used as an ALE signal.
Reads the data from the register of this
controller in "L" level.
Writes D7-D0 in the register of this controller at
the rising edge.
Writes D15-D8 in the register of this controller
at the rising edge.
This is a separate bus in "L" level. This is a
multiplex bus in "H" Level. Fix either "H" or "L"
level.
When the split bus is selected, it functions as
the split data bus.
Notifies the DMA transfer request of D0FIFO
port and D1FIFO port.
Enter the DMA acknowledgement signal of
D0FIFO port and D1FIFO port.
For FIFO port access write direction: Receives
transmission completion signal as an input
signal from other chips or CPU.
For FIFO port access read direction: Shows
the last transmitted data as an output signal.
Notifies various types of interrupts related to
USB communication by "L" active. Active is by
default "L" active, however it can be changed
to "H" active by modifying the setup value of
INTA bit in the software.
For Host function:
When the controller issues an SOF, outputs an
SOF pulse by "L" active.
For Peripheral function:
When an SOF is detected, outputs an SOF
pulse by "L" active.
Connect crystal oscillator between XIN and
XOUT. Connect external clock signal to XIN in
order to input external clock, and leave open
XOUT.
Function
Confidential
Number
of Pins
16
7
1
1
1
1
1
8
2
2
2
1
1
1
1
1
Being
Reset
(Hi-Z)
(Hi-Z)
Pin Status *5)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
*2)
*3)
*4)
*4)
*4)
*1)
(L)
H
H
H
(Hi-Z)
(Hi-Z)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(H)
*2)
*3)
*4)
*4)
*4)
*1)
H
H
H